The use of electronic packaging having spacer elements (e.g., solder balls) is well known in the art with various examples shown and defined in U.S. Pat. No. 5,519,936 (Andros et al), U.S. Pat. No. 5,435,732 (Angulas et al), U.S. Pat. No. 5,170,931 (Desai et al) and U.S. Pat. No. 5,159,535 (Desai et al), all of which are assigned to the same assignee as the instant invention. These patents are thus incorporated herein by reference.
One particular type of electronic package, as shown in the above four patents, for example, is one which utilizes a thin, flexible circuitized substrate as part thereof. Such a substrate typically includes a thin dielectric layer (e.g., polyimide) having one or more circuit layers (e.g., copper) thereon. As shown in the first two patents above, two conductive layers (which may comprise the signal, power and/or ground layer for the package), if used, may be electrically coupled by what are known in the art as plated-through-holes (pths). Such holes in the dielectric layer include a conductive material (e.g., copper) thereon. Such holes are not necessary, of course, should only a single conductive layer be used. Understandably, the greater the number of conductive layers, the greater the functional capability of the resulting package.
It will be understood from the following that the invention is particularly adapted to electronic packaging of the aforementioned type which include either a thin, flexible circuitized substrate or one of greater thickness such as those comprised of ceramic or the well known fiberglass-reinforced epoxy material known as FR4. Such substrates are typically of considerably greater thicknesses than those of the flexible circuitry type. By way of example, an FR4 substrate (better known as a printed circuit or wiring board) may possess a thickness of about 0.030 inch while a corresponding thin flexible substrate having a thin polyimide dielectric layer and two external conductive layers (e.g., copper) may have a typical thickness of about 0.005 inch to about 0.010 inch. A ceramic substrate having one or more layers of circuitry on an upper surface thereof may possess a thickness of about 0.060 to about 0.080 inch.
The invention as defined herein provides a new and unique method for assembly of such packages and particularly for positioning and securing the very small spacers (preferably solder balls) on and to the package, respectively, so that it can then be electrically coupled to yet another packaging structure as part of an overall larger processing system. The spacers as defined herein are of extremely small size, typically being substantially spherical in shape and having a diameter as small as 0.030 inch and perhaps even smaller. Clearly, the precise positioning and coupling of several of such elements successfully to a circuitized substrate having several conductive sites thereon designed to be coupled to said elements is a major engineering challenge. It is further understood that by the term spacer is meant any electrically conductive element, including for example, solid metal (e.g., copper) balls, as well as solder balls of known solder alloys (e.g., 63:37 tin:lead, wherein the tin comprises approximately sixty-three percent of the total alloy volume) that, when coupled to an underlying substrate, will serve to space the substrate on which these are originally located at a spaced location from the initial substrate. Both substrates may thus be substantially parallel to one another if substantially equal quantity spacers are utilized.
There are various techniques for handling conductive spacer elements for use in electronic packages, particularly where the spacers are solder balls or the like. In U.S. Pat. No. 4,830,264 (Bitaillou et al), for example, solder preforms are located on flux atop individual through holes such that the resulting reflow operation causes the solder to enter the holes to thereby form solder terminals. In U.S. Pat. No. 4,871,110 (Fukasawa et al), an aligning plate is used in combination with suction to "attract solder balls into . . . through-holes". In U.S. Pat. No. 5,118,027 (Braun et al), solder paste is applied to solder balls in an alignment boat prior to positioning the combined paste-ball structures on a receiving substrate. In U.S. Pat. No. 5,159,171, a laser beam is used to reach solder reflow temperatures for solder elements on a circuit pattern. Unreflowed solder is then removed. In U.S. Pat. No. 5,324,569 (Nagesh et al), a stencil is used to position a plurality of solder balls onto a carrier or substrate, while in U.S. Pat. No. 5,439,162 (George et al), solder balls having flux deposited thereon are coupled to underlying conductive pads of a suitable substrate.
It is believed that a method for precisely aligning and positioning a plurality of extremely small conductive spacers onto associated conductor pads of a substrate which can be accomplished in a relatively easy manner while using structures of relatively simple yet effective construction would represent a significant advancement over the known art, including particularly the methods described in the foregoing six patents mentioned immediately above. It is further believed that a carrier for receiving and holding such spacers in a substantially fixed pattern relatively to one another to thus enable relatively facile connection to a receiving circuitized substrate would also constitute a significant art advancement.